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I doubt that TriMedia is a Harvard architecture CPU, since it separates only the data memory interface from the instruction memory interface, while keeping the actual data and instruction storage in the same module (SDRAM). In the definition of the Harvard architecture both the storage and interfaces are to be split. In fact, according to the definition of Von Neumann architecture the storage is combined, and nothing is said about the interfaces. Therefore, I'd propose to change the definition of TriMedia into "TriMedia is a Von Neumann architecture CPU with separated data and instruction memory interfaces. TriMedia features many ..." Terechko 14:02, 29 December 2006 (UTC)
I say it is a Harvard architecture CPU because the Instruction and Data cache are entirely seperated in the design. The point where we seem to have a difference of opinion is on how far the code and data memory infrastructure have to be separated to qualify as Harvard architecture. I get the impression that in your view only a complete separation qualifies. In my opinion only a separation of L1 caches is needed. Hennessey and Patterson on page 55 (2nd edition) support my view although they do indicate that that is different than the original meaning.