Talk:SSSE3

what do the instructions do?

I've inserted a summary from the manual; for the scaled-multiply, I've rewritten it to be a bit clearer as to the actual intent of the instruction than the real manual was. User:Fivemack

SSE4 (GNI)

We now know that the actual name for what we thought was "SSE4" is SSSE3, but there seems to be a real SSE4 coming up, as can be read here: SSE4 to debut at Intel show. "SSE4" currently redirects to this page, which is probably the right thing to do until Intel officially declares SSE4 as the name for the next instruction set extension, but I think we should have an article talking about "Gesher New Instructions" at least. I don't have an account, so I've created a request for article creation at Wikipedia:Requested articles/Applied arts and sciences/Computer science, computing, and Internet--213.46.128.161 11:12, 26 September 2006 (UTC)

Addendum: the name is now official--213.46.128.161 21:41, 27 September 2006 (UTC)

Speedy Deletion?

Of course not! Read up on microprocessor instruction sets and please let an article develop before barging in. Anon2 23:13, 10 April 2006 (UTC)

What do the instructions do?

"PABSB" doesn't really say much.

I second this. Why is it so hard to find ISA specs online?

Good question. Why not ask Paul Otellini? Guy Harris 05:03, 18 September 2006 (UTC)

Comparison to Altivec?

Now that Woodcrest is "in the wild", has anyone seen a thorough comparison of Core2 SSE4 vs PPC970 Altivec? What instructions are better/worse/missing on a cycle-for-cycle bit-for-bit basis? Frankie

Having some background here, it looks like PSHUFB would allow for a better mapping with vperm, which has been sorely inadequate in SSE for a long time. AltiVec still has a better instruction coverage (AltiVec went for the approach of, "what is everything that we could possibly want?", while Intel has gone for the approach of, "what do we have to add now?") Obviously, this leads to some frustration, AltiVec was pretty good the first version out the gate, while SSE has taken awhile to get useful, and now requires so many codepaths to be coded for it, that you end up with a jump table to setup specially crafted code for each level of support, if you're going to have a high-speed don't-compile-it-yourself approach. --Puellanivis 00:33, 6 October 2006 (UTC)

WARNING!

SSE4 is - according to intel - NOT THE CORRECT NAME! intel calls it "Meron New Instructions" (MNI). Translated quote from THG: "The Core 2 comes with an extension of SSE3, that Intel internally calls MNI (Meron New Instructions). The name SSE4 is not correct."

"Merom New Instructions" (not "Meron") is just a code name, not an "official" name; the original SSE, for example, was called "Katmai New Instructions"[1]. I don't see anything in the Tom's Hardware article to indicate that Intel have officially said SSE4 isn't going to be the official name. They might have another name for it when they officially announce it, but I suspect it'll be something such as "Intel Ultra Video Technology" or some such noise out of the marketing department, or maybe they'll consider it part of "Intel Advanced Digital Media Boost(TM)" [2], although that appears mainly to be widening data paths(?) to run 128-bit instructions in one clock cycle rather than in two clock cycles, one for the upper 64 bits and one for the lower 64 bits. Or maybe there aren't enough new instructions for them to call it anything.... Guy Harris 22:02, 14 July 2006 (UTC)

Or maybe there aren't enough new instructions for them to call it anything.... What's funny here, is that SSE3 had plenty of a reason to be called supplemental rather than incremental, but yet this is the one that gets supplemental? Maybe Intel works backwards. A "supplemental" set of instructions is actually the first one should have been in the first place? --Puellanivis 00:35, 6 October 2006 (UTC)

SSE4 Compilers

Need to some talk about SSE4 compilers, anyone know of any?

Compilers with SSSE3 auto-vectorization? I don't know any yet. How I write SSSE3 code? Yasm. Pengvado 23:01, 12 October 2006 (UTC)

The latest Intel C-Compiler (ICC 10.1) can have SSE4.1 as a target. Don't know if it will do anything nifty though. MX44 (talk) 17:46, 2 June 2008 (UTC)

More info needed about the new Instructions

The new instruction set is an excellent part of this article, but I feel that an explination of their basic function would be appropriate. I've looked around Intels Website, googled, etc and can find nothing. JimXugle 00:13, 13 September 2006 (UTC)

That might explain why there's no explanation of their basic function. :-) (I.e., if Intel's not saying what they do, it's somewhat hard for somebody to describe what they do, short of reverse-engineering them. I've no idea why Intel doesn't put some obvious documentation on them, as it's a bit hard to use them without knowing what they do.) Guy Harris 08:54, 13 September 2006 (UTC)

Timeline

3DNow! Pro came after SSE. this should be changed on all affected pages.

Wasn't "3DNow! Pro" just a mearketing term for the inclusion of the increasingly popular Intel SSE extension? MX44 (talk) 17:39, 2 June 2008 (UTC)

Yes; I've removed "3DNow! Pro" from the end of the article summary. C xong (talk) 23:16, 15 March 2010 (UTC)

SSSE3

sorry i added something, but i missed the extra s. the AMD doesn't have SSSE3. Markthemac 22:33, 14 August 2007 (UTC)

Citation

Added a citation to this Wikipedia article, citing the "Intel® 64 and IA-32 Architectures Optimization Reference Manual". Let me know if I did it wrong? Furchild (talk) 00:57, 23 June 2018 (UTC)