Talk:IBM POWER architecture

Whoops, moved page incorrectly from "POWER" to "Power".

Hey, I moved the first few of these pages incorrectly due to an error in the POWER1 article. Undo requires admin priviledges, I believe. InternetMeme (talk) 22:37, 29 June 2013 (UTC)

Nope, I was able to undo the renames, because the redirect pages they created had no history. Guy Harris (talk) 02:53, 30 June 2013 (UTC)

Good work there. Thanks! InternetMeme (talk) 10:17, 1 July 2013 (UTC)

Power ISA confusion

I added this. Should the new Power ISA take over this page? comp.arch (talk) 10:01, 22 August 2016 (UTC)

No. Power ISA is not POWER ISA, so there will be no "taking over". By all means, create a Power ISA page, but since those are different things, they should be separate articles.

Since POWER ISA is a historical, hasn't been developed since the early 1990s (the last version was the ISA in POWER2++), this article should be considered historical and not incorporate new things that isn't POWER ISA. -- Henriok (talk) 16:56, 22 August 2016 (UTC)

Ok, so the difference is in the capitalization, not whether ISA is spelled out or not.. Still, I'm not sure you should have reverted.. Anyway, shouldn't this page explain at the top, "not to be confused with Power ISA".. even if there is not page on it? comp.arch (talk) 17:06, 22 August 2016 (UTC)

The PowerPC page says

The PowerPC specification is now handled by Power.org where IBM, Freescale, and AMCC are members. PowerPC, Cell and POWER processors are now jointly marketed as the Power Architecture. Power.org released a unified ISA, combining POWER and PowerPC ISAs into the new Power ISA v.2.03 specification and a new reference platform for servers called PAPR (Power Architecture Platform Reference).

How much of the stuff that's different between the POWER ISA and the PowerPC ISA was incorporated into the Power ISA? The Power ISA 2.03 specification, Appendix A, is called "Incompatibilities with the POWER Architecture", and it lists a bunch of instructions from the POWER ISA not included in Power ISA (I think they were removed when PowerPC was created, although there may have been some processors that implemented the PowerPC ISA but also included some or all of those instructions). It also lists a couple of instructions from the POWER2's version of the POWER ISA that are in the Power ISA, but with some changes, and has a list of POWER2 ISA instructions not carried over into the Power ISA. Were those two instructions that are in the Power ISA also in the PowerPC ISA? Guy Harris (talk) 17:22, 22 August 2016 (UTC)

To answer [your question in the edit summary]. I do not know.. but PowerPC simplified, to make a micropocessor possible. I do not see a reason for them to drop instructions since then, making incompatibility. Does anyone for later [micro] CPUs/arch? comp.arch (talk) 18:05, 24 August 2016 (UTC)

The question wasn't about dropping instructions, it was about adding instructions (or other facilities) back, i.e. some POWER instructions were removed in PowerPC - were any of those added back later?

I think that some instructions were removed in the second generation of the PowerPC chips, but were never part of the PowerPC specification, they were just in the first generation because it was rushed to market. I think the first generation was just a POWER chip modified to be compatible with the PowerPC specification(but without removing POWER instructions). — Preceding unsigned comment added by 173.95.184.204 (talk • contribs) 01:11, 1 January 2017 (UTC)

Yes, the PowerPC 601 was based on the RISC Single Chip, which was a POWER ISA chip, and the 601 kept some of the non-PowerPC POWER instructions. But, as I noted, this was about whether any of the instructions that were removed from POWER when PowerPC was defined were ever added back to PowerPC/Power ISA. As far as I know, that didn't happen. Guy Harris (talk) 02:57, 1 January 2017 (UTC)

But the answer to my question above appears to be "yes, they were in the PowerPC version at least as far back as 2.01"; they're the fctiw and fctiwz instructions, which were called fcir and fcirz in the POWER2 ISA. They behave differently in Power ISA - and probably behave, in the PowerPC ISA, the same way they behave in the Power ISA; to quote The Fine Power ISA 2.03 Manual:

• fcir and fcirz set the high-order 32 bits of the target FPR to 0xFFFF_FFFF, while fctiw and fctiwz set them to an undefined value.
• Except for enabled Invalid Operation Exceptions, fcir and fcirz set the FPRF field of the FPSCR based on the result, while fctiw and fctiwz set it to an undefined value.
• fcir and fcirz do not affect the VXSNAN bit of the FPSCR, while fctiw and fctiwz do.
• fcir and fcirz set FPSCRXX to 1 for certain cases of “Large Operands” (i.e., operands that are too large to be represented as a 32-bit signed fixed- point integer), while fctiw and fctiwz do not alter it for any case of “Large Operand”. (The IEEE standard requires not altering it for “Large Operands”.

so those instructions don't appear to be anything that the Power ISA added as part of "combining POWER and PowerPC ISAs".

The Power ISA 2.03 manual says, quite explicitly, "The MQ is not defined in the Power ISA.", so there's definitely a significant part of the POWER ISA that was not "combined" as part of the process of "combining POWER and PowerPC ISAs" - there's code that'll run on POWER ISA processors that's not guaranteed to run on Power ISA processors - so I'm not sure what "combined" means here. Guy Harris (talk) 19:09, 24 August 2016 (UTC)

I looked up "fcir", and found on page 1355 ("A.32.3 Floating-Point Conversion to Integer"[1]), and note it's in "Appendix A. Incompatibilities with the POWER Architecture", so while there are a few incompatibilities (not just dropped instructions), I think we can say there are such examples, and let this article cover Power and POWER (and PowerPC?), renaming POWER->Power, as the distinction is lost on most people reading WP article title (and separate WP pages for both is not allowed).

"POWER" is now historical, and I do support documenting that history, e.g. not in detail, just as a footnote. These instructions must be userspace (kernelspace instruction changes are a different story), and I've not heard of similar changes to other ISA (at least for the same reason, going from multi-chip). I guess ARM 26-bit->32-bit might qualify, and similar. Thumb-only CPUs are also a special case, a subset of the full arch..

If anyone is reading that can change then there's a typo: "Embedded Guest Perforamnce Monitor Interrupt"->"Performance" comp.arch (talk) 19:56, 25 August 2016 (UTC)

I.e., you're saying "have a single page covering all the various ISA flavors, including the POWER/POWER2 family and the mostly-but-not-completely-compatible-with-the-POWER/POWER2-family PowerPC/Power ISA family"? Guy Harris (talk) 20:43, 25 August 2016 (UTC)

Yes, unless you think it's not a good idea (or just a lot of work to change this and other(?) WP pages). WP doesn't have to reflect all gory details, I think mentioning that there were dropped instructions (doesn't have to be an exhaustive list) and a few changed, is ok. E.g. appropriate this page for the current/future ISA, keeping historical (none of those pre-PowerPC machines are running(?), except possibly in musemums) info in case of [external] links to this page.. comp.arch (talk) 11:30, 26 August 2016 (UTC)

Are we in agreement that there are differences between POWER ISA, PowerPC ISA and Power ISA? I'm interpreting this discussion as "Yes".

Should we have separate articles for each? I vore yes. How do you vote? -- Henriok (talk) 08:47, 30 August 2016 (UTC)

No, not all of us are; I'm not, for example. There are definitely differences between the POWER ISA and the others; however, I haven't seen anything to indicate that the Power ISA isn't just a rename of the PowerPC ISA, so that the 2.02 version of that ISA was called version 2.02 of the "PowerPC ISA" and the 2.03 version of that ISA was called version 2.03 of the "Power ISA" - new stuff may have been added in v2.03, but new stuff appears to have been added in v2.02 as well. I.e., I haven't seen any indication that there were changes between PowerPC ISA v2.02 and Power ISA v2.03 that were any more significant than changes between, for example, PowerPC ISA v2.01 and PowerPC ISA v2.02 or between Power ISA v2.03 and Power ISA v2.04. Guy Harris (talk) 16:49, 30 August 2016 (UTC)

The Power ISA 2.03 is a combination and unification of the different previous PowerPC versions, including new stuff not previously parts of any PPC spec. PPC 1.1, PPC 2.02 and Book E are not the same. AltiVec and an APU segment wasn't a part of the PPC spec itself until Power ISA 2.03. Since then, there's additions concerning virtualisation, decimal floating point, the vector-scalar floating point and transactional memory. Version 3 seems to be IBM and OpenPOWER alone, and I don't know if NXP/Freescale/Power.org was even consulted in any way. I haven't studied it at all besides some new functions like Altivec 3, random number generation and quad-floats. With Power ISA some backwards compatibility regarding PowerPC was broken, but that hasn't happened since. Power ISA v.3 has support for everything called Power ISA. There's clearly a lot of stuff in Power ISA that's never been a proper part of PowerPC. I don't know the specifics though. Why isn't PowerPC 1.1 compatible cores like 750 and 604 considered Power Architecture? I don't know. If we undertake such an investigation, there will be a lot of original research… but PPC 1.1 is _not_ Power. -- Henriok (talk) 20:07, 30 August 2016 (UTC)

"The Power ISA 2.03 is a combination and unification of the different previous PowerPC versions" What, other than combining the "general-purpose computing" versions and the "Book E" version, were combined and unified?

"including new stuff not previously parts of any PPC spec" That just means "it's 2.03"; v2.02 presumably had stuff that wasn't in any previous PPC spec, either, but it was called "PowerPC", not "Power ISA". Adding new features doesn't, by itself, make something a new ISA, it makes it a new version of the existing ISA.

"With Power ISA some backwards compatibility regarding PowerPC was broken". The things I see when searching for "PowerPC" in the 2.03 spec are:

section 5.9.3.2 Bridge to SLB Architecture, which is a change to the way "segmentation" is handled;

section 6.3 Processor State After Reset, where the start address is different.

So it's less of a compatibility loss than the change from POWER to PowerPC (where all the MQ register stuff was lost, for example).

My inclination might be to have a single page to cover all three ISAs, starting with the stuff in IBM POWER Instruction Set Architecture, then giving the stuff from PowerPC#Design features with more details on what was added and what was removed, as well as mentioning the whole Book E thing, and possibly giving information on various of the numbered versions of the PowerPC ISA, and then giving the stuff from Power Architecture#Description (with duplicate stuff removed, all three ISAs being RISC ISAs with 32 GPRs, 32 FPRs, condition code registers, etc.).

Another possibility might be to have a history page giving the history all the way from the pre-history of the POWER ISA to the latest version of the Power ISA, giving all the stuff that changed from POWER to PowerPC, the Book E split and un-split, etc., etc., etc., and another page discussing the current Power ISA in more detail. Guy Harris (talk) 22:19, 30 August 2016 (UTC)

I'd prefer four pages, one for each ISA concentrating on the technical stuff on their own terms, and one with them combined focusing on their development and history. -- Henriok (talk) 21:15, 31 August 2016 (UTC)

And the PowerPC ISA page would indicate that it's based on the POWER ISA, with stuff removed and added, and the Power ISA page would indicate that it's 99 44/100% the PowerPC ISA, with a few incompatible changes and stuff added, presumably. Guy Harris (talk) 21:23, 31 August 2016 (UTC)

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