Mukta Ghate Farooq is an Indian metallurgical engineer of Marathi descent working for the IBM Corporation in Hopewell Junction, New York. She was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2016[1] for her contributions to 3D integration and interconnect technology. She is currently a Distinguished Research Staff Member at IBM Research and has over 220 issued US patents including patent numbers 10199315, 20180061749, and 8367543.[2][3] In 2017, IIT Bombay awarded her the notable alumna award[4]
Mukta Ghate Farooq | |
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Education
editMuktha received her B.Tech. degree in Metallurgical Engineering from IIT Bombay in 1983. Farooq got her master's degree from Northwestern University in Materials Science in 1985 and got her Ph.D. in Materials Science from Rensselaer Polytechnic Institute in 1988.[5]
Distinctions
editDr. Mukta Ghate Farooq was recognized for numerous achievements throughout her educational career, including the Gold Medal Award for undergraduate achievements from the Indian Institute of Foundry (1982), the Dorab Tata Scholarship award (1983), the J.N. Tata Endowment Scholarship (1983), and the IBM Fellowship Award for doctoral studies (1986 - 1988). In 1988, she was nominated to Alpha Sigma Mu, a professional honor society affiliated with ASM International.[6]
In her professional career, Farooq received the Best Paper Award at the IMAPS International Conference (2006), the Technology All Star Award from National Women of Color in STEM (2008),[7] and was designated an IEEE EDS Distinguished Lecturer in 2012. In 2014, she became an IBM Lifetime Master Inventor and was appointed to the IBM Academy of Technology. She also received the Outstanding Technical Achievement Award for 3D Technology Integration in 2015.[6]
In 2016, Dr. Farooq was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).[1] Shortly thereafter, in 2017, she was awarded Bombay's Distinguished Alumnus/Alumna Award from her undergraduate institution, the Indian Institute of Technology Bombay.[4] In 2016, she was named a GLOBALFOUNDRIES Fellow.[8]
Works
editAs of 2022, Farooq was the author of 227 granted U.S. patents,[2] earning her a place on the List of Prolific Inventors. She has also authored a number of lectures, conference papers, and journal articles on subjects including heterogeneous integration for artificial intelligence,[9] 3D TSV integration[10][11] and Pb-free ceramic ball grid array (CBGA) assemblies.[12][13]
References
edit- ^ a b "2016 elevated fellow" (PDF). IEEE Fellows Directory. Archived from the original (PDF) on 23 December 2015.
- ^ a b US Patents of Mukta Farooq
- ^ "Mukta Ghate Farooq Inventions, Patents and Patent Applications - Justia Patents Search". patents.justia.com. Retrieved 30 March 2019.
- ^ a b "IIT Bombay 58th Foundation Day: Honours 11 as Distinguished Alumnus Awards, 2 as Young Alumnus Achievers Awards". 11 March 2017.
- ^ "Dr. Mukta Ghate Farooq | Alumni and Corporate Relations". www.iitb.ac.in. Retrieved 30 March 2019.
- ^ a b "Dr. Mukta Ghate Farooq | Alumni and Corporate Relations". www.alumni.iitb.ac.in. Retrieved 20 January 2021.
- ^ "Plenary & Invited Speakers | PROGRAM". IEEE. Retrieved 20 January 2021.
- ^ "What It Takes to be a Patent Leader | GLOBALFOUNDRIES". www.globalfoundries.com. 3 May 2017. Retrieved 20 January 2021.
- ^ Farooq, Mukta (2020). "Enabling AI with heterogeneous integration". Chip Scale Review. Retrieved 19 January 2021.
- ^ Farooq, M. G.; Graves-Abe, T. L.; Landers, W. F.; Kothandaraman, C.; Himmel, B. A.; Andry, P. S.; Tsang, C. K.; Sprogis, E.; Volant, R. P. (December 2011). "3D copper TSV integration, testing and reliability". 2011 International Electron Devices Meeting. pp. 7.1.1–7.1.4. doi:10.1109/IEDM.2011.6131504. ISBN 978-1-4577-0505-2. S2CID 42496282.
- ^ Farooq, Mukta G.; Iyer, Subramanian S. (5 May 2011). "3D integration review". Science China Information Sciences. 54 (5): 1012. doi:10.1007/s11432-011-4226-7. ISSN 1869-1919.
- ^ Farooq, M.; Goldmann, L.; Martin, G.; Goldsmith, C.; Bergeron, C. (2003). "Thermo-mechanical fatigue reliability of Pb-free ceramic ball grid arrays: Experimental data and lifetime prediction modeling". 53rd Electronic Components and Technology Conference, 2003. Proceedings. New Orleans, Louisiana, USA: IEEE. pp. 827–833. doi:10.1109/ECTC.2003.1216385. ISBN 978-0-7803-7791-2. S2CID 110096776.
- ^ Interrante, M.; Coffin, J.; Cole, M.; De Sousa, I.; Farooq, M.; Goldmann, L.; Goldsmith, C.; Jozwiak, J.; Lopez, T.; Martin, G.; Van Thanh Troung (2003). "Lead-free package interconnections for ceramic grid arrays". IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. San Jose, CA, USA: IEEE. pp. 85–92. doi:10.1109/IEMT.2003.1225883. ISBN 978-0-7803-7933-6. S2CID 108495051.