Interrupt request

In a computer, an interrupt request (or IRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, an interrupt handler, to run instead. Hardware interrupts are used to handle events such as receiving data from a modem or network card, key presses, or mouse movements.

Diagram about the course of an interrupt routine

Interrupt lines are often identified by an index with the format of IRQ followed by a number. For example, on the Intel 8259 family of programmable interrupt controllers (PICs) there are eight interrupt inputs commonly referred to as IRQ0 through IRQ7. In x86 based computer systems that use two of these PICs, the combined set of lines are referred to as IRQ0 through IRQ15. Technically these lines are named IR0 through IR7, and the lines on the ISA bus to which they were historically attached are named IRQ0 through IRQ15 (although historically as the number of hardware devices increased, the total possible number of interrupts was increased by means of cascading requests, by making one of the IRQ numbers cascade to another set or sets of numbered IRQs, handled by one or more subsequent controllers).

Newer x86 systems integrate an Advanced Programmable Interrupt Controller (APIC) that conforms to the Intel APIC Architecture. Each Local APIC typically support up to 255 IRQ lines, with each I/O APIC typically support up to 24 IRQ lines.

During the early years of personal computing, IRQ management was often of user concern. With the introduction of plug and play devices this has been alleviated through automatic configuration.

Overview

When working with personal computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the system BIOS and recognized by the operating system. These default settings can be altered by advanced users. Modern plug and play technology has not only reduced the need for concern for these settings, but has also virtually eliminated manual configuration.

x86 IRQs

Early PCs using the Intel 8086/8088 processors only had a single PIC, and are therefore limited to eight interrupts. This was expanded to two PICs with the introduction of the 286 based PCs.

Typically, on systems using the Intel 8259 PIC, 16 IRQs are used. IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master passes the signal on to the CPU. There are therefore only 15 interrupt request lines available for hardware.

On APIC with IOAPIC systems, typically there are 24 IRQs available, and the extra 8 IRQs are used to route PCI interrupts, avoiding conflict between dynamically configured PCI interrupts and statically configured ISA interrupts. On early APIC systems with only 16 IRQs or with only Intel 8259 interrupt controllers, PCI interrupt lines were routed to the 16 IRQs using a PIR (PCI interrupt routing) table integrated into the BIOS. Operating systems such as Windows 95 OSR2 may use PIR table to process PCI IRQ steering; later, the PIR table has been superseded by the ACPI _PRT (PCI routing table) protocol. On APIC with MSI systems, typically there are 224 interrupts available.

The easiest way of viewing this information on Windows is to use Device Manager or System Information (msinfo32.exe). On Linux, IRQ mappings can be viewed by executing cat /proc/interrupts or using the procinfo utility.

Master PIC

• IRQ 0 – system timer (cannot be changed)
• IRQ 1 – keyboard on PS/2 port (cannot be changed)
• IRQ 2 – 8259 interrupt controller; cascaded signals from IRQs 8–15
• IRQ 3 – serial port controller for serial port 2 (shared with serial port 4, if present)
• IRQ 4 – serial port controller for serial port 1 (shared with serial port 3, if present)
• IRQ 5 – parallel port 3 or ISA sound card
• IRQ 6 – floppy disk controller
• IRQ 7 – parallel port 1 (shared with parallel port 2, if present). It can also be potentially be shared with a secondary ISA sound card with careful management of the port.

Slave PIC

• IRQ 8 – real-time clock (RTC)
• IRQ 9 – Advanced Configuration and Power Interface (ACPI) system control interrupt on Intel chipsets. And/or left for the use of peripherals (use depends on OS)
• IRQ 10 – The interrupt is left for the use of peripherals (for example, SCSI or NIC)
• IRQ 11 – The interrupt is left for the use of peripherals (for example, SCSI or NIC)
• IRQ 12 – mouse on PS/2 port
• IRQ 13 – CPU co-processor or integrated floating point unit or inter-processor interrupt (use depends on OS)
• IRQ 14 – primary ATA channel (ATA interface usually serves hard disk drives and CD drives)
• IRQ 15 – secondary ATA channel

Conflicts

In early IBM-compatible personal computers, an IRQ conflict is a once common hardware error, received when two devices were trying to use the same interrupt request (or IRQ) to signal an interrupt to the Programmable Interrupt Controller (PIC). The PIC expects interrupt requests from only one device per line, thus more than one device sending IRQ signals along the same line will generally cause an IRQ conflict that can freeze a computer.

For example, if a modem expansion card is added into a system and assigned to IRQ4, which is traditionally assigned to the serial port 1, it will likely cause an IRQ conflict. Initially, IRQ 7 was a common choice for the use of a sound card, but later IRQ 5 was used when it was found that IRQ 7 would interfere with the printer port (LPT1). The serial ports are frequently disabled to free an IRQ line for another device. IRQ 2/9 is the traditional interrupt line for an MPU-401 MIDI port, but this conflicts with the ACPI system control interrupt (SCI is hardwired to IRQ9 on Intel chipsets); this means ISA MPU-401 cards with a hardwired IRQ 2/9, and MPU-401 device drivers with a hardcoded IRQ 2/9, cannot be used in interrupt-driven mode on a system with ACPI enabled.

In some conditions, two ISA devices could share the same IRQ as long as they were not used simultaneously. To solve this problem, the later PCI bus allows for IRQ sharing. PCI Express does not have physical interrupt lines, and uses Message Signaled Interrupts (MSI) to the operating systems if available.

See also

• Advanced Programmable Interrupt Controller (APIC)
• Programmable Interrupt Controller (PIC)
• Intel 8259
• Interrupt handler
• Plug and play
• Polling
• Interrupt

Further reading

• Gilluwe, Frank van. The Undocumented PC, Second Edition, Addison-Wesley Developers Press, 1997. ISBN 0-201-47950-8
• Shanley, Tom; Anderson, Don (1995). Swindle, John (ed.). ISA System Architecture (3 ed.). Mindshare, Inc. / Addison-Wesley Publishing Company. ISBN 0-201-40996-8. ISBN 978-0-201-40996-3. [1]
• Solari, Edward. PCI & PCI-X Hardware and Software Architecture & Design, Sixth Edition, Research Tech Inc., 2004. ISBN 0-9760865-0-6

External links

• Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1, chapter 6 – more information on Intel 64 and IA-32 interrupt handling
• Ralf Brown's Interrupt List