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Programmable metallization cell

(Redirected from CBRAM)

The programmable metallization cell, or PMC, is a non-volatile computer memory developed at Arizona State University. PMC, a technology developed to replace the widely used flash memory, providing a combination of longer lifetimes, lower power, and better memory density. Infineon Technologies, who licensed the technology in 2004, refers to it as conductive-bridging RAM, or CBRAM. CBRAM became a registered trademark of Adesto Technologies in 2011.[1] NEC has a variant called "Nanobridge" and Sony calls their version "electrolytic memory".

Description

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PMC is a two terminal resistive memory technology developed at Arizona State University. PMC is an electrochemical metallization memory that relies on redox reactions to form and dissolve a conductive filament.[2] The state of the device is determined by the resistance across the two terminals. The existence of a filament between the terminals produces a low resistance state (LRS) while the absence of a filament results in a high resistance state (HRS). A PMC device is made of two solid metal electrodes, one relatively inert (e.g., tungsten or nickel) the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between them.[3]

Device operation

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The resistance state of a PMC is controlled by the formation (programming) or dissolution (erasing) of a metallic conductive filament between the two terminals of the cell. A formed filament is a fractal tree like structure.

Filament formation

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PMC rely on the formation of a metallic conductive filament to transition to a low resistance state (LRS). The filament is created by applying a positive voltage bias (V) to the anode contact (active metal) while grounding the cathode contact (inert metal). The positive bias oxidizes the active metal (M):

M → M+ + e−

The applied bias generates an electric field between the two metal contacts. The ionized (oxidized) metal ions migrate along the electric field toward the cathode contact. At the cathode contact, the metal ions are reduced:

M+ + e− → M

As the active metal deposits on the cathode, the electric field increases between the anode and the deposit. The evolution of the local electric field (E) between the growing filament and the anode can be simplistically related to the following:

 

where d is the distance between the anode and the top of the growing filament. The filament will grow to connect to the anode within a few nanoseconds.[4] Metal ions will continue to be reduced at the filament until the voltage is removed, broadening the conductive filament and decreasing the resistance of the connection over time. Once the voltage is removed, the conductive filament will remain, leaving the device in a LRS.

The conductive filament may not be continuous, but a chain of electrodeposit islands or nanocrystals.[5] This is likely to prevail at low programming currents (less than 1 μA) whereas higher programming current will lead to a mostly metallic conductor.

Filament dissolution

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A PMC can be "erased" into a high resistance state (HRS) by applying a negative voltage bias to the anode. The redox process used to create the conductive filament is reversed and the metal ions migrate along the reversed electric field to reduce at the anode contact. With the filament removed, the PMC is analogous to parallel plate capacitor with a high resistance of several MΩ to GΩ between the contacts.

Device read

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An individual PMC can be read by applying a small voltage across the cell. As long as the applied read voltage is less than both the programming and erasing voltage threshold, the direction of the bias is not significant.

Technology comparison

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CBRAM vs. metal-oxide ReRAM

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CBRAM differs from metal-oxide ReRAM in that for CBRAM metal ions dissolve readily in the material between the two electrodes, while for metal-oxides, the material between the electrodes requires a high electric field causing local damage akin to dielectric breakdown, producing a trail of conducting defects (sometimes called a "filament"). Hence for CBRAM, one electrode must provide the dissolving ions, while for metal-oxide RRAM, a one-time "forming" step is required to generate the local damage.

CBRAM vs. NAND Flash

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The primary form of solid-state non-volatile memory in use is flash memory, which is finding use in most roles formerly filled by hard drives. Flash, however, has problems that led to many efforts to introduce products to replace it.

Flash is based on the floating gate concept, essentially a modified transistor. Conventional flash transistors have three connections, the source, drain and gate. The gate is the essential component of the transistor, controlling the resistance between the source and drain, and thereby acting as a switch. In the floating gate transistor, the gate is attached to a layer that traps electrons, leaving it switched on (or off) for extended periods of time. The floating gate can be re-written by passing a large current through the emitter-collector circuit.

It is this large current that is flash's primary drawback, and for a number of reasons. For one, each application of the current physically degrades the cell, such that the cell will eventually be unwritable. Write cycles on the order of 105 to 106 are typical, limiting flash applications to roles where constant writing is not common. The current also requires an external circuit to generate, using a system known as a charge pump. The pump requires a fairly lengthy charging process so that writing is much slower than reading; the pump also requires much more power. Flash is thus an "asymmetrical" system, much more so than conventional RAM or hard drives.

Another problem with flash is that the floating gate suffers leakage that slowly releases the charge. This is countered through the use of powerful surrounding insulators, but these require a certain physical size in order to be useful and also require a specific physical layout, which is different from the more typical CMOS layouts, which required several new fabrication techniques to be introduced. As flash scales rapidly downward in size the charge leakage increasingly becomes a problem, which led to predictions of its demise. However, massive market investment drove development of flash at rates in excess of Moore's Law, and semiconductor fabrication plants using 30 nm processes were brought online in late 2007.

In contrast to flash, PMC writes with relatively low power and at high speed. The speed is inversely related to the power applied (to a point, there are mechanical limits), so the performance can be tuned.[6]

PMC, in theory, can scale to sizes much smaller than flash, theoretically as small as a few ion widths wide. Copper ions are about 0.75 angstroms,[7] so line widths on the order of nanometers seem possible. PMC was promoted as simpler in layout than flash.[6]

History

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PMC technology was developed by Michael Kozicki, professor of electrical engineering at Arizona State University in the 1990s.[8][9][10][11][12][13][14] Early experimental PMC systems were based on silver-doped germanium selenide glasses. Work turned to silver-doped germanium sulfide electrolytes and then to the copper-doped germanium sulfide electrolytes.[4] There has been renewed interest in silver-doped germanium selenide devices due to their high, high resistance state. Copper-doped silicon dioxide glass PMC would be compatible with the CMOS fabrication process.

In 1996, Axon Technologies was founded to commercialize the PMC technology. Micron Technology announced work with PMC in 2002.[15] Infineon followed in 2004.[16] PMC technology was licensed to Adesto Technologies by 2007.[6] infineon had spun off memory business to its Qimonda company, which in turn sold it to Adesto Technologies. A DARPA grant was awarded in 2010 for further research.[17]

In 2011, Adesto Technologies allied with the French company Altis Semiconductor for development and manufacturing of CBRAM.[18] In 2013, Adesto introduced a sample CBRAM product in which a 1 megabit part was promoted to replace EEPROM.[19]

NEC developed the so-called nanobridge technology, using Cu2S or tantalumpentoxide as dielectric material. Hereby copper (compatible with copper metallization of the IC) makes the copper to migrate through Cu2S or Ta2O5 making or breaking shorts between the copper and ruthenium electrodes.[20][21][22][23]

The dominant use of this type of memory are space applications, since this type of memory is intrinsically radiation hard.

See also

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References

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  1. ^ "Adesto Technologies Trademarks". Archived from the original on 2019-11-18. Retrieved 2015-07-30.
  2. ^ Valov, Ilia; Waser, Rainer; Jameson, John; Kozicki, Michael (June 2011). "Electrochemical metallization memories-fundamentals, applications, prospects". Nanotechnology. 22 (25): 254003. Bibcode:2011Nanot..22y4003V. doi:10.1088/0957-4484/22/25/254003. PMID 21572191. S2CID 250920840.
  3. ^ Michael N. Kozicki; Chakravarthy Gopalan; Murali Balakrishnan; Mira Park; Maria Mitkova (August 20, 2004). "Nonvolatile memory based on solid electrolytes" (PDF). Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference. IEEE. pp. 10–17. doi:10.1109/NVMT.2004.1380792. ISBN 0-7803-8726-0. S2CID 2884270. Archived from the original (PDF) on July 11, 2016. Retrieved April 13, 2017.
  4. ^ a b M.N. Kozicki; M. Balakrishnan; C. Gopalan; C. Ratnakumar; M. Mitkova (November 2005). "Programmable metallization cell memory based on Ag-Ge-S and Cu-Ge-S solid electrolytes". Symposium Non-Volatile Memory Technology 2005. IEEE. pp. 83–89. doi:10.1109/NVMT.2005.1541405. ISBN 0-7803-9408-9. S2CID 45696302.
  5. ^ Muralikrishnan Balakrishnan; Sarath Chandran Puthen Thermadam; Maria Mitkova; Michael N. Kozicki (November 2006). "A Low Power Non-Volatile Memory Element Based on Copper in Deposited Silicon Oxide". 2006 7th Annual Non-Volatile Memory Technology Symposium. IEEE. pp. 111–115. doi:10.1109/NVMT.2006.378887. ISBN 0-7803-9738-X. S2CID 27573769.
  6. ^ a b c Madrigal, Alexis (October 26, 2007). "Terabyte Thumb Drives Made Possible by Nanotech Memory". Wired. Archived from the original on May 11, 2008. Retrieved April 13, 2017.
  7. ^ "Ion Sizes of Common Elements". Archived from the original on 2007-11-07., compare with Co
  8. ^ "Programmable metallization cell structure and method of making same".
  9. ^ "Programmable sub-surface aggregating metallization structure and method of making same".
  10. ^ "Programmable microelectronic devices and method of forming and programming same".
  11. ^ "Programmable conductor memory cell structure and method therefor".
  12. ^ U.S. Patent 7,372,065
  13. ^ "Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same".
  14. ^ B. Swaroop; W. C. West; G. Martinez; Michael N. Kozicki; L.A. Akers (May 1998). "Programmable current mode Hebbian learning neural network using programmable metallization cell". ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187). Vol. 3. IEEE. pp. 33–36. doi:10.1109/ISCAS.1998.703888. ISBN 0-7803-4455-3. S2CID 61167613.
  15. ^ "Micron Technology Licenses Axon's Programmable Metallization Cell Technology". Press release. January 18, 2002.
  16. ^ "Axon Technologies Corp. Announces Infineon as New Licensee of Programmable Metallization Cell Nonvolatile Memory Technology". Design And Reuse.
  17. ^ "Adesto Technologies Wins DARPA Award to Develop Sub-Threshold Non-Volatile, Embedded CBRAM Memory". Press release. Adesto. November 29, 2010. Retrieved April 13, 2017.
  18. ^ Altis et Adesto Technologies annoncent un partenariat sur les technologies Mémoires CBRAM avancées – Business Wire – published 27 June 2011 - viewed 28 March 2014 Archived 31 March 2014 at the Wayback Machine
  19. ^ "Adesto's CBRAM targets 70 billion dollar market". Nanalyze. July 30, 2013. Retrieved April 13, 2017.
  20. ^ Sakamoto, Toshitsugu; Banno, Naoki; Iguchi, Noriyuki; Kawaura, Hisao; Sunamura, Hiroshi; Fujieda, Shinji; Terabe, Kazuya; Hasegawa, Tsuyoshi; Aono, Masakazu (2007). "A Ta2O5 solid-electrolyte switch with improved reliability": 38–39. doi:10.1109/VLSIT.2007.4339718. S2CID 38195904. {{cite journal}}: Cite journal requires |journal= (help)
  21. ^ "NEC: Nanobridge could build programmable ICs". Retrieved 2020-10-22.
  22. ^ "Low-power FPGA based on NanoBridge®technology" (PDF). Retrieved 2020-10-22.
  23. ^ "Semiconductor device".
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