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Summary
| Description | Layout of NMOS and PMOS components in an OR Gate. This OR gate is implemented as an AND gate with both inputs inverted(by using PMOS at the top) as well as the output (inverter at the right) which is functionally correct, but is not commonly used as it requires 2 extra transistors. |
| Date | |
| Source | Own work using: Inkscape 0.43 |
| Author | inductiveload |
| SVG development |  This circuit diagram was created with Inkscape. |
Licensing
|
I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 18:24, 21 January 2020 | | 375 × 250 (4 KB) | GKFX | Use <text> rather than text as path to give better thumbnails |
| 19:25, 24 March 2014 |  | 375 × 250 (21 KB) | Wereldburger758 | Valid SVG now. | |
| 19:40, 12 July 2006 |  | 375 × 250 (29 KB) | Inductiveload | {{Information |Description=Layout of NMOS and PMOS components in an OR Gate |Source=Own drawing, Inkscape 0.43 |Date=12/07/06 |Author=inductiveload |Permission=PD |other_versions= }} Category:CMOS |
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